The field of the invention is that of CMOS processing, in particular integration of the process for fabricating integrated circuits.
As dimensions shrink in integrated circuit processing, vertical dimensions shrink as well as transverse onesxe2x80x94i.e. the layers that make up the integrated circuit become thinner.
The result of this is that various steps that were straightforward in larger-dimension processing become more difficult.
For example, the dimensions of devices in the near future are expected be less than 110 nm and the gate dielectric in a field effect transistor is expected to be of material having a higher dielectric constant than silicon dioxide (SiO2, oxide). Unfortunately, such materials are less thermally stable than oxide, so that the permissible exposure of the device to high temperatures is even more limited than it is with oxide gate insulators.
It is nevertheless necessary to expose the wafer, and thus the materials within the transistors, to temperatures in excess of one thousand degrees Centigrade in order to activate the source and drain diffusions of the transistors. Most high-k dielectrics can not withstand exposure to such temperatures for the durations required.
Further, the use of metal gates (e.g. Tungsten, Tantalum Silicon Nitride (TaSiN), Tantalum Nitride (TaN)) is accepted as being necessary for adequate transistor performance.
Such gates require a sacrificial gate process, independently of whether the gate dielectric does. In a sacrificial gate process, the transistor is constructed with a dummy, or sacrificial, gate during the steps such as providing alignment of the sources and drains with the gate structure. After activating the source and drain, the sacrificial gate material is removed and the high-k gate dielectric and/or the metal gate material are deposited.
Those skilled in the art are aware that no removal process is one hundred percent efficient, and there will inevitably be removal of extra material, so that the final dimensions of the gate will not be exactly as desired.
In addition, in the case of silicon on insulator wafers, the thickness of the silicon device layer decreases, and there is not enough material in the thickness of the layer to be consumed (e.g. less than about 50 nm of silicon) in the process of forming a silicide for higher conductivity and better performance.
Those skilled in the art are aware that raised sources and drains provide extra thickness only in the sources and drains, while retaining the desired dimension elsewhere.
Although various aspects of the foregoing considerations are known to those skilled in the art, there remains a considerable problem of process integration to make all the process steps produce the desired final result.
It is not enough to combine a step from one solution to a given problem with a step from another solution to another problem if the different steps are mutually exclusive or otherwise conflict.
In integrated circuit processing at the 70 nm node, it is accepted in the art that a sacrificial gate process is necessary. In such a process, the transistor structure is formed
The invention relates to a process for forming a CMOS transistor in a silicon on insulator wafer that combines a sacrificial gate process with a raised source and drain.
In one embodiment of the invention, a three layer hardmask protects the gate stack during subsequent processing.
In one embodiment of the invention, two disposable spacers are used to define the area for the raised source/drain and to block an ion implant into the raised source/drain.
In another embodiment of the invention, the hard mask prevents the formation of silicide on the top of the gate stack.